1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a semiconductor device manufacturing method suitable for use in manufacturing particularly a photoelectric conversion device wherein an insulating layer and a photoconductive semiconductor layer are formed in association with a photoelectric conversion region, a charge storage region for storing an output of the photoelectric conversion region, and a switch region connected to the charge storage region.
2. Related Background Art
Conventionally, as a reader system of a facsimile, with an image reduction optical system and a CCD sensor of semiconductor device has been used. Following the development of photoconductive semiconductor material, a typical example of which is amorphous silicon hydride (hereinafter abbreviated as a-Si:H), a so-called contact type line sensor of semiconductor device has been developed extensively, wherein a photoelectric conversion region and a signal processing region are formed on an elongated substrate to read an original document with an equal magnification optical system.
Particularly, an a-Si:H can be used not only as photoelectric converting material but also as semiconductor material of field effect transistors. Therefore, the photoconductive semiconductor layer of a photoelectric conversion region and the semiconductor layer of a driving element region (signal processing region) can be formed at the same time. Thus, it is possible to provide a photoelectric conversion device having a plurality of elements each having a photoelectric conversion region and a driving element region both formed integrally on the same substrate.
FIG. 1 is a partial cross sectional vertical view showing the structure of a line sensor as an example of a semiconductor device.
As shown in FIG. 1, there are formed on a substrate 1 a wiring region 2, photoelectric conversion region 3, charge storage region 4, and switch region 5. Formed on the substrate 1 are an underlying electrode wiring 6 in the wiring region 2, an underlying electrode wiring 7 in the charge storage region 4, and an underlying electrode wiring 8 serving as the gate electrode in the switch region 5. An insulating layer 9 is formed on these underlying electrode wiring layers 6, 7 and 8. A semiconductor layer (a-Si:H) 11 is formed on the insulating layer 9 in the switch region 5, whereas a photoconductive semiconductor layer (a-Si:H) 10 of photoconductive material is formed on the substrate 1 in the photoelectric conversion region 3. In this case, &he semiconductor layer 11 and photoconductive semiconductor layer 10 are formed at the same time.
A matrix wiring is formed between the underlying electrode wiring 6 and an overlying electrode wiring 12 with an insulating layer interposed therebetween. The photoconductive semiconductor layer 10 and the semiconductor layer 11 are connected by an overlying electrode wiring 13 which runs above the insulating layer 9 in the charge storage region 4. The overlying electrode wiring 13, insulating layer 9 and underlying electrode wiring 7 constitute a storage capacitor. A portion of the overlying electrode wiring 13 connected to one end of the semiconductor layer 11 serves as the drain electrode, and a portion of an overlying electrode wiring 14 connected to the other end of the semiconductor layer 11 serves as the source electrode.
The structure described above has the photoelectric conversion region and signal processing region on the same substrate. As shown in FIG. 1, the semiconductor layer is formed only in the photoelectric conversion region 3 and switch region 5. The insulating layer 9, and the photoconductive semiconductor layer 10 and semiconductor layer 11 on the insulating layer are formed by a film forming method such as glow discharge, and patterned by means of photolithography similar to the case of patterning the overlying and underlying electrode wirings.
FIG. 2 is a schematic plan view showing another example of a line sensor wherein although only two bit elements are shown, the actual line sensor has 1728 bits in total (corresponding to an A4 size readable length, with the density of 8 elements per mm).
FIG. 3 is a partial cross sectional vertical view of the line sensor shown in FIG. 2, wherein an n.sup.+ layer shown in FIG. 4E is omitted for the sake of brevity.
FIGS. 4A to 4E are schematic cross sectional vertical views along line A--A' of FIG. 2 showing conventional line sensor manufacturing steps. FIGS. 4D' and 4E' corresponding to FIGS. 4D and 4E are schematic cross sectional lateral views along line B--B' of FIG. 2.
FIGS. 4A to 4E' differ from FIG. 3 in that an n.sup.+ layer is shown and the insulating layer is removed from a wiring region 102.
The manufacturing method of the line sensor in FIG. 3 will be described with reference to FIGS. 4A to 4E'.
A glass substrate (manufactured by Corning Company Ltd. #7059) whose opposite sides were polished was washed in an ordinary manner using neutral detergent (or organic alkali based detergent).
Cr was deposited to the thickness of 500 .ANG. by the sputter method. Al was then deposited to the thickness of 500 .ANG. by the sputtering method.
A photoresist pattern of desired configuration was formed using a positive type photoresist (Tokyo Ohka NMD-3). Thereafter, an unnecessary portion of Al was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1: in volume ratio.
Next, an unnecessary portion of Cr was etched using an aqueous solution of a mixture of ammonium cerium (IV) nitrate and perchloric acid, to thereby form underlying electrode wirings 106, 107 and 108 in wiring region 102, charge storage region 104 and transfer switch region 105, respectively (FIG. 4A).
Next, the glass substrate 100 was set in a capacitive coupling type glow discharge decomposer which was maintained at 230.degree. C. and at a vacuum pressure of 1.times.10.sup.-6 Torr. SiH.sub.4 diluted to 10% with H.sub.2 was introduced into the decomposer at a flow rate of 5 SCCM, and at the same time NH.sub.3 was introduced therein at a flow rate of 20 SCCM. A glow discharge was effected for 2 hours at an RF discharge power 15 W using a high frequency power source at 13.56 MHz, to thus form an insulating layer 109 made of silicon nitride to the thickness of 0.3 micron. Next, SiH.sub.4 was introduced at the flow rate of 10 SCCM and a glow discharge was effected for 5 hours at the discharge power 8 W and at a gas pressure 0.07 Torr, to thus form an amorphous silicon intrinsic layer 110 to the thickness of 0.50 micron. Subsequently, using as a raw material a gaseous mixture of SiH.sub.4 diluted to 10% with H.sub.2 and PH.sub.3 diluted to 100 ppm with H.sub.2 at a mixture ratio of 1:10, an ohmic contact n.sup.+ layer 115 was deposited to the thickness of 0.12 micron at a discharge power 30 W (FIG. 4B).
Next, a contact hole pattern was formed using a positive type photoresist (Tokyo Ohka NMD-3). Unnecessary portions of the n.sup.+ layer and amorphous silicon intrinsic layer were etched by means of the chemical dry etching method (CDE method) with CF.sub.4 gas to thus form a contact hole 116. In this case, there is no need of selective etching among the n.sup.+ layer, photoconductive semiconductor layer and insulating layer. (FIG. 4C).
Next, Al was deposited to the thickness of 1.0 to 1.5 micron by the sputtering method, to form a conductive layer. Succeedingly, after forming a photoresist pattern of desired configuration, the exposed conductive layer was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio, to thus form an overlying electrode. Thereafter, the exposed n.sup.+ layer was dry etched by means of the reactive ion etching method (RIE method) with CF.sub.4 gas, to thus form the n.sup.+ layer into a desired configuration (n.sup.+ etching process). Next, the photoresist was removed (FIGS. 4D and 4D').
Next, a photoresist pattern was formed for isolating each element.
Thereafter, unnecessary portions of the intrinsic semiconductor layer and insulating layer were dry etched by means of the RIE method with CF.sub.4 gas. As a result, respective elements integrally coupled and electrically connected via the photoconductive semiconductor layer were made independent and separate (isolation process) and only the necessary electrode wirings were used for electrical connection. Next, the photoresist was removed (FIGS. 4E and 4E').
Next, a passivation film (not shown) was formed using silicon nitride by the CVD method, organic resin by coating method, or the like, to thus complete an optical sensor array.
In the line sensor of semiconductor device described above, the patterning of overlying electrode Al is performed through wet etching so that the resist pattern design takes a side etching amount into consideration. However, since the following process of etching the n.sup.+ layer is performed by the RIE method, i.e., anisotropic etching, if the resist pattern for the Al patterning is used as a mask, the design values are not satisfied sufficiently. Thus, in a semiconductor device requiring a highly densed pattern, a problem associated with a sensor characteristic may occur.